Electric drive motor logic control system



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59 7 BY flazzcazz 3. QzzzzpeZ/ ATTORNEY- United States Patent 3,477,002 ELECTRIC DRIVE MOTOR LOGIC CONTROL SYSTEM Duncan B. Campbell, Santa Barbara, Calif., assignor to General Motors Corporation, Detroit, Mich., a corporation of Delaware Filed Oct. 27, 1966, Ser. No. 589,927 Int. Cl. H02 1/42, 3/18; H02k 17/02 U.S. Cl. 318-227 13 Claims ABSTRACT OF THE DISCLOSURE A motor power supply includes a logic control system for controlling the torque and speed of a motor of the type used in vehicle propulsion systems. The logic control system includes analog and digital circuits for developing motor power pulses having a controlled duty cycle and frequency. A timing pulse generator synchronizes the operation of the logic circuits and controls the frequency at which power pulses are applied to the motor. A duty cycle control circuit controls the duration of the power pulses in response to the desired motor power output. An internal clock circuit controls the repetition rate of power pulses which are developed between timing pulses. The logic system also incorporates a pulse delay feature so that a predetermined dead time is developed between shutoff of one power pulse and turn-on of the next power pulse.

This invention relates to an electric drive motor logic control system. More particularly, the invention relates to an analog-digital logic system for a variable speed motor supplied by power pulses having a controlled duty cycle and repetition rate.

With recent improvement of controlled rectifier elements it is possible to design motor control circuits utilizing a power inverter to produce precisely controlled pulses to a motor from a direct current source. These power inverters are designed to handle high current values and, therefore, to supply motors having high power ratings such as are required in vehicular electric drive systems. The controlled rectifier elements, while conducting relatively high currents, are controlled with low power signals from a logic control including static switching elements. The analog-digital logic circuit of this invention produces gating signals to the rectifier elements of a power inverter which in turn supplies multiphase power pulses to an induction motor. The logic circuit controls the motor speed and power output in response to manual command and a source of synchronizing timing signals provided in accordance with the motor speed and operating characteristics.

One of the objects of this invention is to provide a logic control circuit in a motor power supply for producing power turn-on and shut-off gating signals which are applied to a power inverter to produce controlled multiphase motor power pulses having variable pulse duration and occurring at a variable frequency.

A further object of this invention is to provide an analog-digital logic control circuit in a variable speed motor power supply to control the motor power output by providing signals to first, vary the power pulse repetition frequency in response to both externally supplied synchronizing timing pulses and internally produced free running clock pulses having variable frequencies and, secondly, to vary the duration of motor pulses and thus the motor torque by a duty cycle control circuit.

A still further object of this invention is to provide an analog-digital logic control circuit for producing low power gating signals to a power inverter having a variable frequency and variable duty cycle output in response first, to sources of both synchronizing timing pulses and variable frequency clock pulses and, secondly, in response to a duty cycle control circuit controlling the inverter pulse duration by comparing a desired duty cycle signal to the actual inverter pulse duty cycle whereby the duty cycle is maintained constant with changes in frequency when the selected desired duty cycle signal is held constant.

A still further object of this invention is to provide a motor power supply circuit synchronized by timing pulses occurring at a frequency dependent upon the motor frequency plus a programmed slip frequency which during selected speed ranges is held constant or is varied to thereby increase the maximum motor power output. The timing pulses are capable of producing power turn-on and shut-oft signals, synchronizing internal clock signals of variable frequency, and also synchronizing a multiphase switching sequence produced by a power inverter. The synchronization of internal clock signals is provided concurrently with the switching from one phase to the next so that the clock signals supply symmetrical excitation to each motor phase winding.

A still further object of this invention is to provide a logic control circuit for supplying controlled gating signals to a power inverter in which the logic circuit is synchronized by timing pulses occurring in a frequency dependent upon combined motor frequencies and programmed slip frequencies. The timing pulses synchronize controlled rectifier elements of the inverter by synchronizing the gating signals in a three phase switching sequence every 60 electrical degrees. The inverter turn-on and shutoff gating signals are controlled by logic signals which include programmed delay periods between consecutive gating signals during predetermined motor ranges. Also the gating signal sequence is controlled whereby a shutoff signal must be provided before a turn-on signal and conversely a turn-on signal must be supplied before a shut-off gating signal can be applied.

A still further object of this invention is to provide a motor power supply circuit for controlling a vehicle electric drive motor in response to manually controlled motor power command signals and a source of timing pulse signals having an output frequency corresponding to the drive motor speed frequency plus a controllable slip frequency to increase the maximum available vehicle drive torque when the vehicle power source has a given maximum power capability.

And, a still further object of this invention is to provide a logic control circuit for controlling a power inverter producing three phase voltage pulses to a vehicle drive motor wherein the voltage pulses have a variable duty cycle and frequency responsive to logic timing signals. The timing signals have a frequency corresponding to the motor speed frequency and an added predetermined slip frequency. Manual logic command signals combined with the timing signals control and synchronize separate frequency determining and pulse width or duty cycle controlling logic circuits to thereby control the average voltage supplied to the drive motor. The logic circuits are controlled in accordance with signals proportional to motor voltage and speed so that the average motor excitation voltage is determined by pulses having predetermined variable frequencies, variable durations or predetermined combinations of both variable frequency and pulse duration.

In the drawings:

FIGURE 1 is a block diagram of a motor supply sysstem utilizing a logic circuit made in accordance with this invention for controlling a power inverter.

FIGURE 2 illustrates a graph of the motor torque and horsepower outputs of a motor controlled by a logic circuit made in accordance with this invention.

FIGURE 3 is a graph of a programmed slip frequency utilized in the logic circuit of this invention to provide the 3 motor output power and torque shown in the graph of FIGURE 2.

FIGURE 4 is a schematic diagram of a logic control circuit made in accordance with this invention.

FIGURE 5 is a block diagram of a circuit for producing a variable delay pulse utilized in the logic circuit made in accordance with this invention.

FIGURE 6 is a graph of the variation of pulse width with changes in motor speed provided in the circuit shown in FIGURE 5.

FIGURE 7 is a graph of wave forms of signals at various points in the circuit shown in FIGURE 4.

Referring now to the drawings and more particularly to FIGURE 1 wherein a diagram is shown of a motor power supply utilizing a logic circuit 10 of this invention. External logic input control signals are connected to the logic circuit 10 from a control source shown generally at 12 and a timing pulse generator 14. The output of the logic circuit 10 is connected to the gate electrodes of an inverter circuit 16 having semiconductor controlled rectifiers with power supplied from DC source 18. This inverter preferably is of a type disclosed and claimed in copending application S.N. 589,927, filed concurrently herewith and now abandoned in which the inverter circuit includes six power controlled rectifiers. Power pulses of Timing signals are supplied from the timing pulse generator 14 to synchronize the logic circuit operation and to control the gating signals applied to the inverter 16 so that the controlled rectifiers are switched in a three phase sequence. A three phase voltage appears at the motor input and passes through Y connected windings 28, and 32 With changes in phase occurring every 60 electrical degrees. The phase voltage is applied as one polarity for 120 degrees, then olf for 60 degrees and then in an opposite polarity for 120 degrees. After another 60 degree off period the cycle is repeated. For example, when a synchronizing timing pulse is supplied from the pulse generator 14 a positive phase voltage is developed across motor winding 28 with a negative phase voltage developed across winding 30 when controlled rectifiers 34 and 36 are gated on. Current from the source 18 is then conducted through the controlled rectifier 34, motor phase windings 28 and 30 and back through the controlled rectifier 36. After 60 electrical degrees the control rectifier 34 continues to conduct but the control rectifier 36 is shut-off by a commutating capacitor means, not shown, and the control rectifier 38 is gated to conduction. Motor current continues to be applied through motor phase winding 28 but current has switched from winding 30 to 32. The remaining controlled rectifiers of the inverter circuit 16 are switched by gating signals from the logic circuit 10 to change motor phase current every 60 electrical degrees so that three phase power pulses are sequentially applied to the motor 20. The detailed operation of the power inverter 16 in response to the logic circuit turn-on and shut-off gating pulses is described in the above-mentioned copending application.

When the motor 20 is connected to drive a vehicle the output power and maximum torque curves are shown in the graphs of FIGURE 2. The maximum torque curve 40 and horsepower curve 42 of motor 20 includes three regions as indicated on the graph. Region I shows an increasing maximum torque with increasing motor speed to a selected point of motor speed. The motor is started from a stalled condition having a predetermined maximum starting torque and increases torque with speed to a predetermined maximum torque limit. The Region II includes a motor speed where the maximum torque is maintained constant with increased motor speed. In the Regions I and II the horsepower curve 42 increases at a rate proportional to the product of torque and speed. Although the curve 42 is shown essentially linear in Regions I and II, it is understood that in practice the rate of increase may not be linear. As the curves extend into Region III the power output 42 of the motor 20 is maintained essentially constant because it is limited by the capacity of the power source 18 which may be a battery, fuel cell or other energy conversion electrical source. Accordingly, as motor speed increases the maximum torque curve 40 decreases.

In FIGURE 3 there is shown a graph of slip frequency which is maintained constant up to a motor speed corresponding to the end of Region II in FIGURE 2 and then is increased to a maximum at a speed which corresponds to end of the motor speed range. By way of example but not limitation, the motor speed may extend from stall to about 12,000 rpm. In copending application S.N. 295,954, now Patent No. 3,323,032, filed July 18, 1963, and assigned to the assignee of this application a constant slip frequency system is disclosed that provides an induction motor with speed-torque characteristics similar to those of a DC series motor. In Region III of FIG. URE 2, a dashed line 44 shows the maximum motor torque and the dash-dot line 45 shows the output power produced if the slip frequency is maintained constant in the motor speed range of Region III. It has been found that by increasing slip frequency the maximum torque is increased and accordingly the motor power and consequently a constant horsepower range can be provided in Region III. Also, the power output of DC source 18 is maintained along its loci of maximum power. The increased slip frequency lowers the motor impedance and the counter which opposes the voltage of source 18. With less opposing voltage the power source voltage is effective in producing more rotor current and thus increased torque. The slip frequency must be limited since the motor losses also increase with increased slip frequency. For example, the constant slip frequency can be provided at a frequency between 4 to 5 c.p.s. in motor speed Regions I and II and then increased to a maximum slip frequency between 10 to 15 c.p.s. The curve of slip frequency shown is determined so there is an optimum increase of torque at the higher motor speeds without serious motor losses when the output voltage and power of the power source 18 are at fixed maximum values.

It is to be noted that in FIGURE 2 the maximum torque curve in Region I is increased from a desired maximum torque at stall to a peak level of maximum torque because at lower motor speeds the motor impedance and counter are low and high reactive currents occur when the motor phase windings are switched. These reactive currents must be limited so as not to exceed the current capacities of the inverter controlled rectifiers. Also when the motor power supply is used in the mechanical drive system of a vehicle, there are inherent vehicle maximum torque limitations when starting from rest. Therefore, it has been found that with a given maximum power source voltage of approximately 500 volts, for example, that an average value of only 20 volts can be applied to the motor at low speeds whereas when the full voltage of 500 volts is applied at high speeds there is produced the same torque. This occurs since the motor counter increases to oppose the power source voltage.

As noted above, the average motor excitation voltage is controlled to vary the motor torque by applying variable frequency and also variable duty cycle power pulses to the motor. The pulse duty cycle refers to the ratio of the power pulse width to the total pulse period or more generally, the ratio of the sum of plural pulse widths to a given time period. The pulse frequency or repetition rate refer-s to the number of power pulses generated in a given period. The basic frequency of the logic circuit, and there-fore, the inverter circuit is determined by the timing pulse generator 14 which provides synchronizing pulses at a frequency equal to six times the combined motor speed, as detected by the tachometer device 26, and a predetermined slip frequency, provided from the external logic control 12.

In brief, to provide the graphs of motor characteristics of FIGURES 2 and 3, inverter gating pulses are supplied from the logic circuit with each timing pulse, at the 60 electrical degree time, and also with internal clock pulses when occurring between the timing pulses. The amplitude of each voltage pulse applied to the motor is determined by the power source 18 but pulse repetition and duration is modulated 'by the logic circuit to control the average pulse voltage. At lowest speeds, control by frequency or repetition rate occurs with between one to ten inverter gating pulses being produced between the 60 electrical degree synchronizing pulses. At slightly higher motor speeds anywhere between one to nine pulses can occur. Smooth transition occurs as motor speed increases through a predetermined speed which, by way of example, may be 1500 r.p.m. where a maximum of four pulses can occur. As the motor speed increases from the selected range of approximately 1500 to 2500 r.p.m., for example, there is a time interval for only three pulses between the 60 electrical degree timing pulses and, accordingly, between a range of 2500 and 5000 r.p.m., for example, two pulses per 60 degree period can be used. Above the 5000 r.p.m. speed only one power pulse will occur per 60 degree period and this power pulse is accordingly produced by each timing pulse. Throughout all speed rang-es the conduction time of the control rectifiers is being varied to vary the duty cycle so that average voltage is controlled by control of both pulse frequency and duration to produce smooth changes in the motor output power.

It is to be kept in mind that while the pulses may be maintained at a given duration, the average voltage applied to the motor will increase with increased frequencies since the pulses will be occurring at increased repetition rates.

Referring now to FIGURE 4 wherein the logic control circuit of this invention is shown, external command signals are applied to the input of the logic circuit from external controls 12. The command signals include safety monitoring input 46 and manually operated signals including on-olf input 48, forward-reverse input 50 and power command 52 which in a vehicle corresponds to throttle position.

The external control 12 includes a source 56 of programmed slip frequency signals fs which are applied to the timing pulse generator 14. The timing pulse generator 14 provides timing signals to the logic circuit at a frequency corresponding to an integral multiple of the combined motor rotor frequency plus slip frequency. The added slip frequency fs and the motor speed frequency fm are conveniently added in the timing pulse generator and also frequency multiplied by a conventional frequency multiplication circuit means to provide a signal six times the frequency of fs plus fm. The pulse frequency output of timing pulse generator 14 occurs at six times the inverter frequency which is the synchronous frequency of the applied motor excitation. Accordingly, a three phase sequence is produced in the inverter 16 in which a "phase change occurs six times during one inverter cycle or every 60 electrical degrees. To provide the phase sequence, timing pulses from generator 14 are generated on output lines 58 with one line being applied to a phase sequence control 60 which includes a binary counting means for producing a three phase sequence. The manual command signals from controls 12 include line 64 which provides a logic control signal to circuit 60 from forward-reverse command input 50 to reverse the phase sequency of the binary counting and thus the inverter phase sequence.

Safety monitoring signals from 46 are combined on line 62 with the on-off command applied at 48 so that logic GO-NO GO signals are provided and in the event of a malfunction the logic will be turned off. Also the GO-NO GO signal may be responsive to an off throttle position, when a throttle position controls the power command. In such a case no logic output signals are produced and the inverter is turned off so that no power from the power source is used. The power command or throttle input 52 is applied to a power command circuit 68 where it is combined with a motor speed signal fm. The motor speed signal is combined with the power command in circuit 68 and a signal is provided on the output lines 66 that is proportional to the desired average motor voltage which accordingly is a function of both the desired power and the motor speed. The motor speed signal fm is also applied to the programmed slip frequency control 56 to vary the slip frequency signal in accordance with the motor speed as explained above. The speed signal fm applied to the power command circuit 68 and the slip frequency circuit 56 may be provided alternatively from point A at the output of timing pulse generator 14 to the circuit junction 72. The timing pulses are sulficiently approximate to the actual motor speed that the point A may be used as a convenient circuit connection from the logic to the junction 72 in providing motor speed reference signals to circuits 56, 68 and a third logic circuit explained in further detail below.

Referring now in further detail to FIGURE 4 and the circuits of the logic control 10 wherein are shown block diagrams of conventional circuits having gating, delay and pulse producing functions known in logic systems and will not be described in detail. For example, the circuit includes AND and OR gating circuits although analogous circuits such as NAND and NOR circuits can be used to perform analogous logic functions. To start and synchronize the logic circuit, timing pulse generator 14 is connected to an AND logic gate 74 along with the GO-NO GO signal from line 62. A GO signal must be present before pulses of the timing pulse generator can be coupled through the gate 74 to line 58. The timing pulses on line 58 are applied to a reset circuit 76, a power control trigger network 78, and as noted above, the phase sequence control 60. The timing pulses applied to reset circuit 76 are connected to the input of a variable pulse Width generator 80 which is described in detail below. The width of the pulses supplied from the variable pulse circuit 80 is determined by a motor speed signal fm which is the third output from junction 72. The output of the reset circuit 76 provides a reset pulse on output lines 82 which is connected to a duty cycle control circuit 84, the power control trigger circuit 78 and an internal clock circuit 86. Synchronization by the reset pulse is provided by simultaneously starting the circuits 84 and 86 and, after a predetermined time delay, producing a turn-on trigger pulse from circuit 78. Also included in the reset circuit '76 is a second pulse generator circuit 88 which may be a monostable multivibrator having a fixed pulse width output and an input supplied from internal clock circuit 86, output line 90, through an AND logic gate 92 and line 93. The GO-NO GO signal from line 62 is applied to AND gate 92 as well as AND gate 74 to enable the gates soas to pass signals only when GO logic command signal is present. The pulse circuit-s 80 and 88 produce a reset pulse 100 on line 82 through OR gate 70 and accordingly it can be seen that the reset circuit 76 will produce a reset pulse from either circuit or both in which case the output pulses will overlap.

The function of the internal clock circuit 86 is to supply variable frequency pulses as feedback pulses to the reset circuit 76 and also as shut off signals to power trigger network 78. Circuit 86 includes a ramp voltage source 94 and a comparator circuit 96. One input to ramp voltage source 94 is the reset pulse 100 from line 82 and the second input is the desired average motor voltage signal from line 66. The leading edge 102 of a reset pulse 100 causes the ramp circuit 94 to reset or return to its starting level. At the trailing edge 104 of reset pulse 100, the voltage is removed and the ramp voltage is released and begins to rise. The desired motor voltage signal from line 66 varies the rate of rise of the ramp voltage developed in the ramp source 94. Comparator 96 receives the ramp voltage applied on line 106 and a clock pulse is generated when the ramp voltage reaches a fixed reference level provided by a voltage on an input line 97 to provide an internal clock pulse on line 90. This clock pulse is applied through the AND gate 92 to the pulse generator 88 in circuit 76 in a closed feed back loop. The internal clock circuit 86, reset circuit 76 and the AND gate 92 form an oscillatory network with clock pulses being produced at variable repetition rates. The repetition rate is varied by the combined duration of the pulse from circuit 88 and the variable rate of rise of the ramp voltage of circuit 94. For example, with a power command signal being applied, the frequency of the pulses varies from 32 c.p.s. to 1400 c.p.s. as the power command input 52 or motor speed increases. At low motor speeds and with a maximum repetition rate up to 10 pulses can be provided between consecutive timing pulses.

Concurrently, reset pulses on line 82 are also applied to the duty cycle control 84. The duty cycle control 84 includes a ramp voltage source 108 producing a ramp voltage having a fixed linear rate of rise. An error detector circuit 10 receives the desired average motor voltage signal from line 66. Since the average voltage is determined by the duty cycle of pulses produced by the inverter, the desired average motor voltage corresponds to the desired duty cycle. The duty cycle error detector 110 includes a conventional dilferential input integrating circuit that compares a signal proportional to the duty cycle of the inverter pulses from line 114 with the desired duty cycle which is proportional to the desired average motor voltage. The difference between these two signals forms an error signal which is integrated with respect to a constant predetermined time period to develop a duty cycle DC reference voltage on line 112. A comparator circuit 116 compares the reference voltage of line 112 with the constant rate of rise ramp voltage on line 118. When the ramp voltage reaches the duty cycle reference voltage of line 112 an output pulse is provided from comparator 116 on line 121 as a shut-off logic signal to power control trigger network 78. A steady state operatlon can be achieved so that zero error exists between the desired motor voltage duty cycle signal on line 66 and actual duty cycle signal on line 114. The shut-offlogic signal from the duty cycle control on line 121 terminates the power pulses so that a constant duty cycle can be maintained depending upon the power command signal. A constant duty cycle provides a constant average voltage. This is controlled in the error detector 110 by integrating the pulse widths which define each duty cycle over a predetermined time period so that the product of integration will remain constant throughout the frequency ranges of the inverter and therefore of the motor, i.e., if the pulse frequency doubles the pulse widths are halved, etc. No matter how asymmetrical the pulse wave may be on line 114, the duty cycle will remain constant for a given desired voltage command on line 66.

Turning now to the output of the logic circuit which is provided by power control trigger network 78 and pulse distribution circuit 130. Network 78 includes a shut-oif pulse generator 120 and a turn on pulse generator 122. Shut-01f trigger pulses are generated on line 124 in response to pulses provided from the AND logic gate 138 and OR gate 126. A shut-off trigger pulse is produced whenever pulses are applied to OR gate 126 from the duty cycle control 84 or the timing pulse generator on line 58 or from the internal clock circuit on line 93. The turn-on pulse generator 122 produces a turn-on trigger pulse on line 128 whenever it receives an input coupled through AND gate 140 from the inverter and differentiating circuit 132 which provides a spike voltage at the trailing edge 104 of the reset pulse 100. The shut off and turn on pulses are respectively applied to lines 124 and 128 and connected to the pulse distribution circuit 130. The pulse distribution circuit 130 includes an arrangement of binary logic circuits which are activated by the pulses from the conventional binary counting circuit and phase sequence control signals within circuit 60. The turn-on and shut-oil. trigger pulses on lines 124 and 128 form turn-on and shut-off gating signals on lines 134 which are connected to the controlled rectifiers within the aforementioned inverter circuit 16.

In order that shut-off and turn-on pulses will not appear without the other pulse having occurred first, a power trigger sequence control is provided by the AND gates 138, 140, and a bistable multivibrator circuit 144. The bistable circuit 144 will change to one logic state whenever a turn-on trigger pulse is generated, and to the other state when a shut-off trigger pulse is generated. The 1 output of bistable 144 is the complement of thetl output such that one of the outputs is at a high voltage level when the other is at a low voltage level. One input to gate is the differentiated and inverted voltage spike from circuit 132 and if the other input, from the 0 output of bistable 144, is high the dilferentiated positive going pulse is coupled to 122 wherein a power turnon trigger is generated. Upon the falling edge of the turnon trigger pulse the bistable multivibrator 144 is set so that the 0 output goes low and AND gate 140' is disabled and also the 1 output of 144 goes high so that AND gate 138 is enabled. The logic pulse signal from the duty cycle control on line 121 is coupled through OR gate 126 to AND gate 138. Since the other input to gate 138 is high, the pulse from line 121 is further coupled to pulse generator 120 wherein a power shutoff trigger is produced. The trailing edge of the shut-off trigger pulse on line 124 resets the bistable multivibrator 144 so that gate 138 is disabled and gate 140 is enabled. The result of this action of bistable multivibrator 144 is to require an alternate gating sequence in the inverter of power turn-on before power shut-off and power shutoff before power turn-on.

In FIGURES 5 and 6 the circuit of variable pulse width generator 80 in the reset circuit 76 is shown in more detail. The circuit includes a function generator 148, a fixed ramp voltage source 150, a DC voltage level comparator 152 and a bi-stable multivibrator circuit 154. The function generator 148 includes a diode-resistance network which develops a voltage wave shape that is proportional to the shape of the curve shown in FIG- URE 6 from the motor frequency signal fm. The curve profile shows first, a downward slope starting at a high value which corresponds to a higher voltage or longer pulse width produced at the output of pulse generator 80. The ramp voltage from source 150 will rise until the reference voltage is reached and the comparator 152 produces a trigger pulse to bistable circuit 154. The output pulse from one output of the bistable 154 is initiated by a timing pulse occurring on line 58 with a second bistable output being connected to the ramp voltage source 150 so that it is unclarnped and starts rising. The output of 154 will return to their original state when the ramp voltage reaches the reference level of function generator voltage. Accordingly, it is seen that the pulse duration of the output from bistable 154, which is applied to OR gate 70, is determined by the voltage level produced in function generator 148.

The voltage output of the function generator is proportional to the graph of FIGURE 6 which indicates that a longer pulse width is programmed at the output of pulse generator 80 at lower motor speeds than at higher motor speeds. The function of the variable pulse is to provide a delay time in the reset pulse 100 pulse width so that the power controlled rectifier elements of the inverter are provided with a time delay or dead time after shut-off as the motor phase current is switched. The first region of FIGURE 6 is a transition from the longest pulse width to a constant region and then a second transition region to the shortest width which remains constant from approximately the middle to the highest motor speeds. The reset pulse 100 provided at the output of OR gate 70 controls the time delay required for proper operation of the inverter. This time delay may be referred to as a dead time which is initiated coincident with either the timing pulses occurring on line 58 or internal clock pulses on line 93 which have a dead time duration dependent upon the pulses from pulse generators '88 or 90 or both if the pulses overlap. This so called dead time allows for the dissipation of reactive motor currents to permissible levels and also the recharging of the inverter commutating circuit. Thus, the delay or dead time starts with a timing pulse or internal clock pulse which will produce a shut-off trigger pulse, if prior thereto there was turn-on trigger, and secondly, start reset of ramp voltages in circuits 84 and 86. At the end of. the dead time occurring at the trailing edge of the reset pulse 100, a turn-on pulse from generator 122 is produced.

In summary, the purpose of the delay provided by the profile of the curve of FIGURE '6 is to control the dead time or period between successive shut-off and turn-on trigger pulses. At low speeds the reactive motor current decays slowly because of low motor impedance. Therefore, if a second pulse is applied too soon the reactive current will not have decayed sufficiently and too large a current will be conducted by the inverter control rectifier. The inverter will then be required to shut off a very high current whereas if the pulses are sufliciently spaced the current being shut-off will be lessened. As the motor speed increases toward the mid-speed range the reactive current is decreased but sufiicient delay must be allowed to permit the inverter commutating circuit to recycle. After the motor speed reaches the mid-speed range there are no pulses between the timing pulses so that suflicient time is provided for recycling the inverter. The delay time is then rapidly programmed to provide the minimum delay required through the higher motor speeds. It is necessary to keep the dead time at a minimum in the higher speed ranges since this decreases the duty cycle or average voltage supplied to the motor.

The operation of the logic circuit of FIGURE 4 is understood from the wave forms of the various voltages on the lines as indicated in FIGURE 7. A time sequence is shown starting at time T1 with the graph being understood to represent different individual operating conditions during various motor and inverter frequencies. Idealized motor voltage and resulting motor current are shown at the bottom of the FIGURE 7 with voltage signals in the upper graphs showing how control is provided by the logic circuit of this invention.

In the graph of wave forms in FIGURE 7, the lines on which the voltage pulses occur are indicated by number on the left side of the graph and they respectively correspond to the numbers of the lines shown in FIGURE 4. The timing pulses occurring on line 58 are shown at the top of the graph and the first timing pulse at T1 is shown occurring during a high motor speed range where the average voltage applied to the motor is determined by two consecutive timing pulses. In operation, a timing pulse is applied from the pulse generator 14 through the AND gate 74 to lines 58 with the system on so that a G logic signal occurs on line 62. One of the lines 58 is applied to the power trigger circuit OR gate 126 which would supply a shut-01f pulse but it is assumed that the power pulse in the inverter has already been shut-off and therefore no shut-01f pulse will be generated because of the power trigger sequence control of circuit 78 described above. The timing pulse is also applied to the phase sequence control circuit 60 so that a different phase current path will be established in the motor by the timing pulse. Also the timing pulse is applied to the reset circuit 76 and the variable pulse width generator 80 which is reset as described in connection with FIGURE 5 and thereby initiates the leading edge 102 of reset pulse 100. The reset pulse on line 82 is simultaneously applied to the duty cycle control circuit 84 to start reset of the ramp voltage source 108 and the ramp voltage source 94 in internal clock circuit 86. The third output of reset pulse 100 is applied to the differentiating and inverter circuit 132 so that the trailing edge of the reset pulse 132 will trigger generator 122 and provide a turn-on trigger pulse. The duration of the reset pulse 100 determines the delay or dead time as programmed by the function generator 148 of FIGURE 5. When the ramp voltage from source 150 reaches the level of the function generator a comparator pulse will be generated to reset the bistable circuit 154 and provide the trailing edge 104 of the reset pulse 100. This occurs at time T2 in FIGURE 7 and a turn-on trigger is generated on line 128 and is applied to the pulse distribution circuit where it is applied as a turn-on gating signal on lines 134 to turn on a pair of control rectifiers in the inverter circuit. The upward and downward arrows at 134 in FIG- URE 7 indicate turn-on and shut-off gating pulses respectively supplied on lines 134. The trailing edge 104 of the reset pulse also unclamps the internal clock ramp voltage source 94 and duty cycle ramp voltage source 108 so that the voltage ramps are generated at the outputs 106 and 118 respectively. Reference voltages on lines 97 and 112 applied to the comparators 96 and 116 of circuits 86 and 84 respectively are not reached by the respective ramp voltages because a second timing pulse on line 58 occurs at T3. The timing pulse is applied to the power control trigger network gates 126 and 138 to generate a shut-01f trigger pulse from pulse generator 120. A shutoff gating signal at the output 134 of pulse distribution 130 is applied to the inverter to commutate a conducting controlled rectifier to shutoff and terminate the motor voltage pulse at T3. It can be seen that a single voltage pulse will be supplied to the motor between T1 to T3.

At time T3, a timing pulse again occurs on line 58 at the next 60 electrical degree interval of the inverter frequency to initiate a pulse cycle as described for the timing pulse occurring at timing pulse T1. With time T4 the duty cycle ramp voltage on line 118 begins to rise toward the reference voltage on line 112 which has a lower level following T3. The variation of the duty cycle comparator level on line 112 is determined by the integration of the difference between desired duty cycle on line 66 and actual duty cycle on line 114. The wave forms of signals occurring on line 114 are produced by 1 output of bistable circuit 144 and it can be seen that the waveshape of the signals on line 114 has the same duty cycle as the motor voltage power pulses. When the reference level is reached, a pulse to initiate the shut-off trigger from comparator 116 is produced on line 121 at time T5. The motor input voltage pulse width between the times T4-T5 is determined by the duty cycle control circuit 84. Thus, it is seen a shut-off pulse can be generated either by timing pulses on line 58 or duty cycle control pulse on line 121.

Another timing pulse occurs at T6 providing the reset pulse on line 82 to again reset the ramp voltages on lines 106 and 118 and to initiate another power turn-on at T7 after the delay or dead time of circuit 76.

The interval beginning with the timing pulse at T6 corresponds to operation at a lower frequency range when the internal clock circuit 86 is effective to produce additional power pulses between the 60 intervals. The timing pulse at T6 starts a reset pulse 100 on line 82 which terminates at T7 there is a turn-on trigger pulse. The ramp voltages are unclaimed in circuits 94 and 108 and continue to rise with the ramp voltage on 118 reaching the reference level of duty cycle comparator 116 at T8. The ramp voltage 118 continues to rise until a clamp circuit, not shown, acts to limit further rise of the ramp.

A shut'off control pulse is provided on line 121. The internal clock ramp voltage continues to rise on line 106 until T9 when the trigger level of comparator 96- is reached and an internal clock pulse is produced on line 90. The fixed pulse width generator 88 now provides the reset pulse starting at T9. Both the duty cycle ramp and internal clock ramp voltages are reset and a clock pulse from line 90 is applied to the OR gate 126 but no shut-off trigger pulse is produced since a shut-off was previously produced by the duty cycle circuit at T8. The cycle is repeated starting at T10 as started at T7 and ends with an internal clock pulse at T12. The internal clock pulse occurring at T12 again produces the reset function in the fixed pulse width generator 88 starting with the leading edge of the reset pulse on line 82. At time T13 a timing pulse occurs at a 60 interval and an output from variable pulse width generator circuit 80 occurs prior to the end of the pulse from 88 which ends at T14. The two pulses overlap while passing simultaneously through OR gate 70 during T13 to T14. The trailing edge 104 of the reset pulse on line 82 occurs at T15 at the end of the pulse developed by circuit 80. The cycle of pulses between T15 and T is the same as described as occurring between T7 and T12. At T21 the trailing edge of the reset pulse occurs and this reset pulse was initiated by the internal clock pulse occurring at T20 on line 90. At this time a gating pulse starts another output voltage pulse and both ramp voltages are started on lines 106 and 118. At T22 both ramps are reset before either ramp reaches its respective trigger reference voltage since a timing pulse then occurs. This is the same condition that existed at T3 except following T21 the timing pulse at T22 shuts-off a voltage pulse which had been initiated by an internal clock pulse. The pulse cycle again begins to repeat at T23. The internal clock ramp voltage reaches the trigger level of line 97 at T24 before the duty cycle ramp voltage on line 118 reaches its trigger reference level on line 112. This condition may occur at low speeds when the duty cycle error voltage is high and the ramp voltage rate of rise is less than the rate of rise of the internal clock ramp voltage so that the reference level of the internal clock comparator is reached first.

It is seen then that the logic is syncronized by the timing pulses on line 58 and that shut-off trigger pulses from circuit 120 can occur either under the control of the internal clock pulse circuit 86 or the duty cycle control circuit 84 or if the shut-off is not provided by either circuits 86 or 84 a shut off can be provided by the timing pulse which also initiates a new turn-on trigger pulse after the programmed dead time. It can also be seen that there will always be a delay interval between the power shut-off gating pulse and the power turn-on gating pulse as determined by the width or dead time of the reset pulse so that the inverter and motor circuits are conditioned for a new pulse and a change in the phase se-- quence.

While the embodiment of the present invention as herein disclosed constitutes a preferred form it is to be understood that other forms might be adopted.

Iclaim:

1. A logic control circuit for an induction motor power supply producing power pulses from a semiconductor switching circuit having a variable duty cycle and a variable frequency comprising, a motor speed signal source which is responsive to motor speed, a source of slip frequency signals, means coupling said speed signal sources and said source of slip frequency signals whereby said slip frequency signals are a function of said motor speed signal, a timing pulse source connected to be responsive to both said motor speed signal and said slip frequency signal for producing timing signals including a slip frequency component which is increased with increasing motor speed during predetermined speed ranges, a first trigger pulse source coupled to said semiconductor switching circuit and to said 12 timing pulse source for producing a power turn-on switching pulse in response to each timing pulse, a second trigger pulse source coupled to semiconductor switching circuit and to said timing pulse source for producing a power shut-off switching pulse, means responsive to said motor speed signal and coupled to said first trigger pulse source for delaying the time between shut-off and turn-on switching pulses, a clock pulse source including a frequency control circuit connected to respond to said motor speed signal and to be rendered operative by said timing pulses for producing clock pulses at a controllable frequency, means applying said clock pulses to said first and second trigger pulse sources to control the switching frequency of said semiconductor switching circuit between consecutive timing pulses at a rate determined by the frequency of said clock pulses produced by said clock pulse frequency control circuit.

2. A motor control system for a variable speed electric motor comprising, a source of motorpower, a multiphase inverter circuit for applying power from said power source at controllable frequencies to said motor, a source of speed reference signals which are a function of motor speed, gating means for applying control signals to said inverter circuit in a predetermined phase sequence, a source of evenly spaced timing pulses connected to said gating means for controlling the frequency of operation of said inverter and synchronizing the multiphase inverter sequencing operation, a source of clock pulses connected to said gating means, means coupling said source of clock pulses and said source of timing pulses whereby said timing pulses initiate a clock pulse cycle with the occurrence of each timing pulse, said clock pulse source including a feedback circuit including a monostable switching circuit, control means for producing a time varying ramp signal, and a trigger circuit, means coupling said control means and said source of speed reference signals, said ramp signal having a variable rate of rise controlled as a function of the speed of said motor, means connecting said trigger circuit with said switching current and with said control means, said trigger circuit having a reference signal level and operative to produce a pulse which is applied to said monostaple switching circuit when said ramp voltage reaches the value of said reference signal level whereby recurring clock pulses are developed between timing pulses at a rate which is a function of motor speed.

3. A logic control circuit for a vehicle induction drive motor system providing controllable power pulses of variable duty cycle and frequency from a DC voltage source, comprising, a source of motor speed reference signals, a power gating circuit means including a source of power turn-on pulses for initiating a power pulse and a source of shut-off pulses for terminating a power pulse, a source of internal clock pulses, a reset pulse producing circuit responsive to the motor speed reference signals and internal clock pulses and providing pulses of variable duration to said sources of turn-on and shut-off pulses, a pulse duty cycle determining circuit including a source of ramp voltages being initiated by a reset pulse, a feedback circuit producing a duty cycle reference signal related to the difference of a manually operated desired motor voltage signal and a signal proportional to the voltage being supplied to the motor, and a comparator circuit means having inputs connected to the duty cycle reference signal and said ramp voltage source for producing a duty cycle control pulse to said source of shutoff pulses, said internal clock pulse circuit including a source of variable rate of rise ramp voltages initiated by said reset pulses with the ramp voltage rate being controlled by the desired motor voltage signal, a means having a source providing a constant reference signal to produce a pulse signal to said reset pulse circuit when said variable ramp voltage reaches the value of said constant reference signal, said power gating circuit being responsive to a motor speed reference signal or an internal clock pulse to initiate shut-off signals and also responsive to said source of reset pulses so that a turn-on signal is produced at the end of said reset pulse whereby the width of said reset pulse provides a predetermined dead time between turn on and shut-off gating signals.

4. A variable frequency motor power supply system comprising: an electrical power source; an electrical motor for driving a load at both variable speeds and torque; a power control circuit including plural switching devices connected between said power source and said motor for supplying alternating current power pulses having a predetermined duty cycle and a controlled frequency; a trigger control circuit connected to said power switching circuit for gating said switching devices respectively conductive and nonconductive; means for generating a speed reference signal which is a function of motor speed; a timing pulse generator having an output connected to said trigger control circuit for developing a series of timing pulses which control the frequency at which said alternating current power pulses are developing by said power control circuit; means responsive to the duty cycle of power pulses developed by said power control circuit for producing a duty cycle reference signal; a duty cycle control circuit connected to said trigger circuit for controlling the duty cycle of said power pulses, control means providing a command signal which is a function of desired speed and torque output of said motor, means connecting said duty cycle control circuit with said control means and with saidmeans for producing said duty cycle reference signal to thereby control the duty cycle of said power pulses as a function of the relative magnitude of said command signal and said reference signal, a clock pulse generator circuit connected to respond to said timing pulses and to said speed reference signal for generating clock pulses having a repetition rate which varies with motor speed; said trigger control circuit gating said switching devices conductive and nonconductive in response to either of said clock pulses and said timing pulses thereby developing motor power pulses having variable duty cycles and repetition rates for developing desired motor speed and torque outputs.

5. In a motor control system for controlling the frequency and magnitude of voltage applied to an induction motor from a source of voltage through a switching circuit comprised of a plurality of switching elements connected between said source of voltage and said motor comprising, control means coupled to said switching circuit for alternately operating said switching circuit in a conductive mode where said switching circuit is biased conductive to connect said source of voltage and said motor and in a disconnect mode where said switching circuit is biased nonconductive to disconnect said power source and said electrical load whereby said motor is supplied with an alternating voltage having a controlled frequency and average voltage magnitude, means providing a source of timing signals connected with said control means to provide consecutively occurring turn-on and turn-off signals to said control means to thereby determine the frequency of the voltage applied to said motor, said timing signals providing predetermined conduction angles for said switching circuit, and a variable frequency oscillator circuit having an output and an input, means coupled to the output of said oscillator circuit and to said control means for causing said switching circuit to operate alternately between its conductive and nonconductive modes at intervals between said timing pulses to thereby control the average voltage applied to said motor during a given conduction angle, a first source of adjustable reference voltage for controlling operation of said motor, means providing a second reference voltage, and comparator means connected to said reference voltage sources, and to said oscillator circuit, said oscillator circuit operable to provide output pulses which are a function of the relative magnitudes of said reference voltages when said reference voltages have a predetermined relationship, said oscillator circuit developing no output pulses between said timing pulses when said reference voltages have another relationship.

6. In a motor control system for an electric motor, the combination comprising, a switching circuit comprised of a plurality of switching elements connected between a source of electrical power and said motor and operative to control both the frequency and the magnitude of the voltage applied to said motor from said power source, said switching circuit operating in a conductive mode to connect said source of power and said motor and operable in a disconnect mode wherein said switching circuit is biased nonconductive to disconnect said source of power and said motor, a source of timing signals, control means coupled to said source of said timing signals and to said switching circuit for alternately operating said switching circuit in said connect and disconnect modes in accordance with the frequency of said timing signals to thereby control the frequency of the voltage applied to said motor, and means providing first, second and third signal voltages each of which is capable of biasing said switching circuit nonconductive depending upon the order of occurrence of said signals, means providing said first signal voltage in response to the occurrence of a timing signal, a duty cycle detecting means, means providing a duty cycle reference voltage, means coupling said duty cycling detecting means to said control means whereby said duty cycle detecting means responds to the duty cycle of a voltage pulse applied to said motor, means for developing said second signal voltage when the voltage sensed by said duty cycle detecting means has a predetermined relationship with the voltage developed by said duty cycle reference voltage, an oscillator circuit, means coupling said oscillator circuit to a device which provides a first adjustable reference voltage for commanding operation of said motor, means providing a second reference voltage, and means for causing said oscillator circuit to develop said third signal voltage whenever said first and second reference voltages have a predetermined relationship, each of said first, second and third signal voltages being capable of biasing said switching circuit nonconductive when said circuit has been previously biased conductive by another of said signals.

7. The electrical system according to claim 6 where means are provided for controlling the frequency of the timing pulses as a function of the speed of rotation of said motor.

8. In a control system for controlling voltage pulses applied to an electric motor from a source of power through a switching circuit, the combination comprising, control means coupled to said switching circuit for biasing said switching circuit in a conduction mode to connect said source of power and said motor and in a nonconductive mode to disconnect said source of power and said electric motor, a logic control circuit connected to said control means, said logic control circuit including a source of timing pulses coupled to said control means, a given timing pulse when applied to said control means operative to bias said switching circuit to said conduction mode, and means for biasing said switching circuit to a nonconductive mode in response to first, second and third signal voltages following the biasing of said switching circuit to said conduction mode, means coupled to said source of timing signals for providing said first signal voltage in response to the occurrence of a timing pulse, means providing a duty cycle reference voltage, means coupled to said duty cycle reference voltage means and to said control circuit for providing said second signal voltage whenever the duty cycle of a voltage pulse applied to said motor has a predetermined relationship with respect to said duty cycle reference voltage, an oscillator capable of providing said third signal voltage, means for providing an adjust able first reference voltage for commandng operation of said motor, means providing a second reference volt- 15 age, means coupling said oscillator to said reference voltages whereby said oscillator develops said third signal whenever said reference voltages have predetermined relationship, said first, second and third signals operative to bias said switching circuit nonconductive depending upon the order of occurrence of said signal voltages.

9. In an electric vehicle power supply system including a direct power source, an induction drive motor including a three phase input winding and operable over a lower speed range in which the maximum torque characteristic increases with speed, an intermediate speed range in which the maximum torque characteristic is substantially constant, and an upper speed range in which the maximum torque characteristic decreases as motor speed increases, and a three phase inverter circuit including a plurality of semiconductor switches arranged to be gated in conductive pairs every sixty electrical degrees so as to develop alternate polarity power pulses in a three phase sequence, a logic control circuit comprising: means for producing speed reference signals which are a function of motor speed; a power command circuit connected to said speed reference signals for developing a desired motor control voltage signal which is a function of motor speed; a slip frequency control means for developing a signal which is a function of a desired slip frequency at predetermined motor speeds; a timing pulse generating circuit responsive to said speed reference signals and to said slip frequency control signal for producing timing pulses at a frequency six times the combined frequencies corresponding to the speed of said motor and said desired slip frequency; a reset pulse generating circuit including an input connected to said timing pulses and an output for producing a pulse having a predetermined pulse width defined by leading and trailing pulse edges, said reset pulse circuit including means responsive to said speed reference signals for varying the pulse width of said reset pulse as a function of motor speed; a clock pulse circuit for generating pulses which are responsive to said leading edge of said reset pulse, said clock pulse generating circuit being further responsive to said desired motor voltage signal to control the rate at which clock pulses are developed such that the repetition rate is decreased with increased motor speed whereby the number of clock pulses developed between the timing pulses is varied between a predetermined maximum number at low motor speeds to a minimum number at high motor speeds, said clock pulses being connected to said input of said reset pulse generating circuit so that a reset pulse is generated in response to either of said timing and said clock pulses; a shut-off trigger cont-r01 circuit connected to said inverter circuit to render said semiconductor switch pairs nonconductive in response to either of said timing pulses or said clock pulses; a power turn-on trigger control circuit connected to said inverter circuit and responsive to said trailing edge of said reset pulse to gate said semiconductor switch pairs conductive after a dead time which is determined by the pulse width of said reset pulse; circuit means connected to both of said turn-on and shut-off trigger control means for producing a duty cycle reference signal which is responsive to the duty cycle of power pulses developed by said inverter; a duty cycle control circuit responsive to said desired motor voltage signal and to said duty cycle reference signal for producing a duty cycle control signal which is connected to said shut-off trigger control circuit, said shut-off trigger control circuit being responsive to a duty cycle control signal occurring before either of said timing or clock pulses to render said semiconductor switch pairs nonconductive thereby developing power pulses having predetermined duty cycles, whereby the speed of said motor is controlled in response to the frequency of said timing pulses, the torque developed by said motor is predominantly controlled at lower speeds in response to the repetition rate of said clock pulses which are developed between timing pulses and at higher motor speeds motor torque is predominantly controlled in response to the duty cycle control so that Said maximum motor torque characteristics are produced throughout said lower, intermediate and higher speed ranges.

10. In an electrical power supply system for a motor having an input winding which is connected to a source of electrical power by a switching device having a controlled switching rate for controlling the voltage and current which is supplied to said input winding, said power supply system comprising: a trigger control circuit coupled to said switching device for applying turn-on and shut-off triggering signals which are operative to gate said switching device respectively conducting and nonconducting; control means coupled to said trigger control circuit for producing control signals operative to initiate said turn-on and shut-off triggering signals; a programmed timing circuit connected between said control means and said trigger control circuit for producing programmed time intervals between said shut-off and said turn-on triggering signals so that minimum dead time periods are provided between conducting times of said switching device, whereby conducting periods of said switching device are time spaced so that sufficient current decay is provided during said dead time periods to limit the miximum level of current being conducted by said switching device.

11. In an electrical power supply system for a motor having an input winding which is connected to a source of electrical power by a switching device having a controlled switching rate for controlling the voltage supplied to said input winding, said power supply system comprising: a trigger control circuit coupled to said switching device for applying turn-on and shut-off triggering signals which are operative to gate said switching device respectively conducting and nonconducting; control means including a time delay switch circuit coupled to said trigger control circuit; a source of cyclically occurring control signals coupled to said control means, said control means being responsive to a single control signal produced by said source of control signals to generate a pair of successively occurring shut-off and turn-on triggering signals in said trigger control circuit whereby said triggering signals are developed at time spaced intervals which are controlled solely by said time delay circuit, whereby a minimum dead time period is provided between successive conducting periods of said switching device so that current supplied by said switching device to said input winding is limited to predetermined maximum current levels.

12. An electrical power supply system for a motor having an input winding which has an input characteristic such that when a predetermined voltage is applied thereto the input current is reduced as motor speed increases and wherein said input windings are connected to a source of electrical power by a switching device having controlled conducting time periods for controlling the voltage applied to said input windings, said power supply system comprising: a trigger control circuit coupled to said switching device for applying turn-on and shut-off triggering signals which are operative to render said switching device respectively conducting and nonconducting; a pulse generating means connected to said trigger control circuit for producing pulse signals which are operative to develop turn-0n triggering signals which initiate each conducting period of said switching device; a pulse timing control means including a time delay circuit coupled between said pulse generating means and said trigger control circuit; means coupled to said time delay circuit for developing a control signal having a variable magnitude; said pulse timing control means generating a shut-off triggering signal followed by said turn-on triggering signal in response to one of said pulse signals and providing a variable predetermined dead time period between said triggering signals that is controlled by the magnitude of said variable control signal, whereby the amplitude of current being conducted by said switching device is limited to predetermined maximum levels by variable minimum dead time periods which are provided between successive conducting periods of said switching device.

13. An electrical power supply system for controlling a motor having an input winding which conducts varying current amplitudes in response to changes in motor speed when a given voltage is being impressed across said input winding and wherein the input winding is connected to a direct current source by a switching device having controlled conducting time periods for delivering voltage and current to said input winding, said power supply system comprising: a trigger control circuit coupled to said switching device for applying turn-on and shut-off triggering signals which are operative to render said switching device respectively conductive and nonconductive; a pulse generating means connected to said trigger control circuit for producing pulse signals which are operative to develop turn-on triggering signals which initiate each conducting period of said switching device; a voltage control means connected to said trigger control circuit for developing shut-01f triggering signals which control the conducting periods of said switching device and thereby control the average voltage applied to said motor during predetermined time periods; a pulse timing control means including a time delay circuit coupled between said pulse generating means and said trigger control circuit and being operative in respnose to said pulse signals for successively developing in said trigger control circuit a shut-off triggering signal followed by one of said turn-on triggering signals so that said shut-off and turn-on triggering signals are developed at time spaced intervals which are controlled by said time delay circuit; a speed signal source coupled between said motor and said time delay circuit for producing speed signals which are variable in accordance with the speed of said motor and are operative to vary the time spaced intervals between said triggering signals in response to changes in motor speed, so that varying minimum dead time periods responsive to changes in motor speed are provided between successive conducting periods of said switching device thereby limiting the maximum level of current being supplied to said motor by said switching device.

References Cited UNITED STATES PATENTS 3,243,677 3/1966 Cannalte et a1. 3l8231 3,374,413 3/1968 Dornbarger et a1. 318-341 3,393,354 7/1968 Gaither et a1 318-341 ORIS L. RADER, Primary Examiner G. RUBINSON, Assistant Examiner US. Cl. X.R. 

